User Profile

Buildolution

My Profile

A Power Domain

*******

*******, ******* *******

*******

******* ******* *******

What is meant by a Power Domain?A Power Domain is a collection of design elements that share a primary supply set.What is the need of having level shifters in a design?Level shifters are required when multiple voltage domains are present in a design.When a logic signal moves from one voltage domain to another voltage domain,level shifter is used to convert that logic signal from one voltage level to another voltage level so that signal logic value is interpreted properly in different voltage domains.Define the concept of Isolation with respect to Power Domains.Isolation is a technique for controlling behavior of a signal which is driven into or out of a power domain that is powered down.It comprises of clamping the signal to a known value i.e.1,0,or latching it to a previous value when the power domain is powered down.What is meant by metastability?When does it happen and what are its consequences?This usually happens when there are setup and hold time violations.How can metastability be avoided?Metastability can be avoided by using synchronizers in the design.How does a basic synchronizer circuit look like?Draw a sample Synchronizer circuit.Below is an example of a basic synchronizer circuit.What is Clock Gating?It is a technique that is used to control power dissipated by the clock network.This helps in reducing dynamic power consumed by the design by avoiding unnecessary switching activity.What is Power Gating and why is it used?Power gating shuts off static leakage when a logic is not in use,thereby reducing power consumption.Clock gating helps in reducing dynamic power while power gating helps in reducing static power.Destination clock domain may receive incoherent data if proper design techniques are not used.If multiple signals are being transferred from one clock domain to another clock domain such that all these signals are changing simultaneously,and the source and destination active clock edges arrive close to each other,some of these signals may get captured in one clock cycle and some in another clock cycle in destination clock domain,thereby leading to data incoherency.Mention few design techniques that can be used.In such a case,some of these signals may get captured in one clock cycle and some in another clock cycle in destination clock domain leading to data incoherency.Concept of synchronizer is discussed in one of the answers above.In this technique,feedback signal is sent as an acknowledgement signal from destination clock domain to source clock domain.This is one of the safest design techniques as it provides full synchronization independent of clock frequency.Give an example of an issue that can occur while transferring data from a faster clock domain to a slower clock domain.What are the advantages and disadvantages of using an Asynchronous Reset?What are the advantages and disadvantages of using a Synchronous Reset?If the circuit has an internal tristate bus,separate asynchronous reset would be required to prevent bus conflict on internal tristate bus.What is a Reset Recovery Time?What is a frequency synthesizer?Give an example of frequency synthesizer?It is used for performing phase/frequency modulation and demodulation,and can also be used as frequency synthesizer.It is used as a metric for evaluating the progress of a verification project.Coverage metric forms an important part of measuring progress in constrained random testbenches and also provides good feedback to the quality and effectiveness of constrained random testbenches.While code coverage is generated automatically by simulators,Functional coverage is user defined and normally implemented using constructs supported by SystemVerilog language.This section has questions related to the coverage concepts as well as the SystemVerilog language constructs used for implementing functional coverage model.What is the difference between code coverage and functional coverage?There are two types of coverage metrics commonly used in Functional Verification to measure the completeness and efficiency of verification process.Code coverage is automatically extracted by the simulator when enabled.It is also not dependent on the design code as it is implemented based on design specification.What are the different types of code coverage?This is generally considered important and is targeted to be 100%covered for verification closure.In the following example code,you can see there are 4 lines or statements which will be measure in statement/line coverage.Block coverage measures whether these types of block codes are covered during simulation.Block coverage looks similar to statement coverage with the difference being that block coverage looks for coverage on a group of statements.Toggle coverage measures how well the signals and ports in the design are toggled during the simulation run.It will also help in identifying any unused signals that does not change value.Remember that code coverage is automatically extracted by simulator based on a test suite while functional coverage is a user defined metric.A low code coverage number shows that not all portions of the design code are tested well.A high functional coverage number shows that all the functionalities as captured by the user from the test plan are tested well.Either the test plan is not capturing all the design features/scenarios/corner cases or implementation of functional coverage monitors for same is missing.The design code not covered in code coverage could be mapping to this functionality.Hence it is important in the verification project to have proper reviews of the user defined functional coverage metrics and its implementation.What are the two different types of constructs used for functional coverage implementation in SystemVerilog?A covergroup construct is used to measure the number of times a specified value or a set of values happens for a given signal or an expression during simulation.A covergroup can also be useful to measure simultaneous occurrence of different events or values through cross coverage.A covergroup can be defined in a package,module,program,interface,checker,or a class.

A Bamzeno Production, featuring Greytness